1. Field of the Invention
The present invention relates to a pipeline analog-to-digital converter (ADC), and more particularly, to a pipeline analog-to-digital converter that is capable of sharing comparators, and related methods.
2. Description of the Prior Art
Pipeline ADCs are common structures in high speed and high-resolution analog-to-digital converters. Please refer to FIG. 1. FIG. 1 schematically illustrates a 1-bit per stage pipeline analog-to-digital converter 100 according to the prior art. As FIG. 1 shows, an input end of the pipeline analog-to-digital converter 100 is coupled to a sample-hold-amplifier (SHA) 110, and the pipeline ADC 100 comprises a plurality of subsequent stages. FIG. 1 only illustrates two subsequent stages 120-1, 120-2 for simplicity. An input signal Vin is sampled and amplified by the SHA 110 to generate a signal Vin1. Next, the signal Vin1 is fed into the subsequent stages 120-1. At this moment, a comparator 122-1 compares the signal Vin1 with the ground voltage level, so as to generate a digital output D(0). If the signal Vin1 is greater than the ground voltage level, the digital output D(0)=1. On the other hand, if the signal Vin1 is not greater than the ground voltage level, the digital output D(0)=0. Then, the signal Vin1 and the digital output D(0) are fed into a multiplying digital-to-analog converter (MDAC) 124-1 at the same time. The signal Vin1 is amplified by an SHA 126 to generate a signal Va1. The amplified signal Va1 is then inputted to an adder 128-1. If the digital output D(0)=1, the output signal Vout1 of the adder 128-1 is Va1−Vref. On the other hand, if the digital output D(0)=0, the output signal Vout1 of the adder 128-1 is Va1+Vref. The output signal Vout1 is then fed to the subsequent stages 120-2, and a digital output D(1) is outputted after a similar operation of the subsequent stage 120-2 is performed. After a plurality of subsequent stages generate their respective digital outputs, the pipeline analog-to-digital converter 100 combines these digital signals outputted by the subsequent stages, and results in the combined digital signal.
As FIG. 1 shows, in the prior pipeline analog-to digital converter 100, the digital output of every subsequent stage corresponding to each clock cycle of the pipeline analog-to digital converter 100 generates a value. After the inner comparator of each subsequent stage performs a comparison operation, the inner comparator waits for a next input value in order to perform a next comparison operation in a next clock cycle of the pipeline analog-to-digital converter 100. In addition, the multiplying digital-to-analog converter (MDAC) determines the waiting period of the comparator. Because the operation of the MDAC requires a longer time than the operation of the comparator in each clock cycle of the pipeline analog-to digital converter 100, the comparator idles for a significant time. Therefore, if the comparator between two subsequent stages could be shared, the circuit area could be released in order to save power.